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? semiconductor components industries, llc, 2010 june, 2010 ? rev. 2 1 publication order number: ADM1024/d ADM1024 system hardware monitor with remote diode thermal sensing the ADM1024 is a complete system hardware monitor for microprocessor ? based systems, providing measurement and limit comparison of various system parameters. eight measurement inputs are provided; three are dedicated to monitoring 5.0 v and 12 v power supplies and the processor core voltage. the ADM1024 can monitor a fourth power supply voltage by measuring its own v cc . one input (two pins) is dedicated to a remote temperature ? sensing diode. two more pins can be configured as inputs to monitor a 2.5 v supply and a second processor core voltage, or as a second temperature ? sensing input. the remaining two inputs can be programmed as general purpose analog inputs or as digital fan speed measuring inputs. measured values can be read out via a serial system management bus and values for limit comparisons can be programmed in over the same serial bus. the high speed successive approximation adc allows frequent sampling of all analog channels to ensure a fast interrupt response to any out ? of ? limit measurement. the ADM1024?s 2.8 v to 5.5 v supply voltage range, low supply current, and smbus interface make it ideal for a wide range of applications. these include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics. features ? up to nine measurement channels ? inputs programmable ? to ? measure analog voltage, fan speed or external temperature ? external temperature measurement with remote diode (two channels) ? on ? chip t emperature sensor ? five digital inputs for vid bits ? ldcm support ? system management bus (smbus) ? chassis intrusion detect ? interrupt and overtemperature outputs ? programmable reset input pin ? shutdown mode to minimize power consumption ? limit comparison of all monitored values ? this is a pb ? free device applications ? network servers and personal computers ? microprocessor ? based office equipment ? test equipment and measuring instruments http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. ordering information xxx = specific device code #=pb ? free package yyww = date code marking diagram tssop ? 24 case 948h 1024 aruz #yyww 1 pin assignment 1 2 5 6 7 8 9 10 20 21 22 23 24 19 14 13 12 11 sda scl ci fan2/ain2 fan1/ain1 ntest_out/add vid1/irq1 +2.5v in /d2+ +v ccp1 vid4/irq4 gnd v cc reset ntest_in/aout int v ccp2 /d2? +5.0v in d1? d1+ +12v in vid0/irq0 ad1024 (top view) therm vid3/irq3 vid2/irq2 18 17 16 15 3 4
ADM1024 http://onsemi.com 2 figure 1. functional block diagram 10 ? bit adc d1+ d1? gnd ADM1024 ci vid0/irq0 vid1/irq1 vid2/irq2 vid3/irq3 vid4/irq4 fan1/ain1 fan2/ain2 power to chip +v ccp1 +2.5v in /d2+ +5.0v in +12v in v ccp2 /d2? v cc pullups v cc vid0?3 and fan divisor register vid4 and device id register fan speed counter input attenuators and analog multiplexer band gap temperature sensor address pointer register temperature configuration register 2.5v band gap reference serial bus interface channel mode register value and limit registers limit comparators interrupt status registers int mask registers interrupt masking configuration registers analog output register and 8 ? bit dac ntest_out/add int ntest_in/aout therm reset v cc v cc v cc 100k chassis intrusion clear register sda scl 100k 100k 100k absolute maximum ratings parameter rating unit positive supply voltage (v cc ) 6.5 v voltage on 12 v in pin 20 v voltage on aout, ntest_out add, 2.5 v in /d2+ ? 0.3 to (v cc +0.3) v voltage on any other input or output pin ? 0.3 to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t jmax ) 150 c storage temperature range ? 65 to +150 c lead temperature, soldering vapor phase (60 sec) infrared (15 sec) 215 200 c esd rating all pins 2000 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. thermal characteristics package type ja jc unit 24 ? lead small outline package 50 10 c/w
ADM1024 http://onsemi.com 3 pin assignment pin no. mnemonic description 1 ntest_out/add digital i/o. dual function pin. this is a three ? state input that controls the two lsbs of the serial bus address. this pin functions as an output when doing a nand test. 2 therm digital i/o. dual function pin. this pin functions as an interrupt output for temperature interrupts only, or as an interrupt input for fan control. it has an on ? chip 100 k pullup resistor. 3 sda digital i/o. serial bus bidirectional data. open ? drain output. 4 scl digital input. serial bus clock. 5 fan1/ain1 programmable analog/digital input. 0 v to 2.5 v analog input or digital (0 to v cc ) amplitude fan tachometer input. 6 fan2/ain2 programmable analog/digital input. 0 v to 2.5 v analog input or digital (0 to v cc ) amplitude fan tachometer input. 7 ci digital i/o. an active high input from an external latch that captures a chassis intrusion event. this line can go high without any clamping action, regardless of the powered state of the ADM1024. the ADM1024 provides an internal open drain on this li ne, controlled by bit 6 of register 40h or bit 7 of register 46h, to provide a minimum 20 ms pulse on th is line to reset the external chassis intrusion latch. 8 gnd system ground. 9 v cc power (2.8 v to 5.5 v). typically powered from 3.3 v power rail. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 10 int digital output. interrupt request (open ? drain). the output is enabled when bit 1 of register 40h is set to 1. the default state is disabled. it has an on ? chip 100 k pullup resistor. 11 ntest_in/aout digital input/analog output. an active ? high input that enables nand test mode board ? level connectivity testing. refer to the section on nand testing. also functions as a programmable analog output when nand test is not selected. 12 reset digital i/o. master reset, 5 ma driver (open drain), active low output with a 45 ms minimum pulse width. set using bit 4 in register 40h. also acts as reset input when pulled low (e.g., power ? on reset). it has an on ? chip 100 k pullup resistor. 13 d1 ? analog input. connected to cathode of first external temperature ? sensing diode. 14 d1+ analog input. connected to anode of first external temperature ? sensing diode. 15 +12 v in programmable analog input. monitors 12 v supply. 16 +5.0 v in analog input. monitors 5.0 v supply. 17 v ccp2 /d2? programmable analog input. monitors second proce ssor core voltage or cathode of second external temperature ? sensing diode. 18 +2.5 v in /d2+ programmable analog input. monitors 2.5 v suppl y or anode of second external temperature ? sensing diode. 19 +v ccp1 analog input. monitors first processor core voltage (0 v to 3.6 v). 20 vid4/irq4 digital input. core voltage id readouts from the proc essor. this value is read into the vid4 status register. can also be reconfigured as an interrupt input. it has an on ? chip 100 k pullup resistor. 21 vid3/irq3 digital input. core voltage id readouts from the proce ssor. this value is read into the vid0?vid3 status register. can also be reconfigured as an interrupt input. it has an on ? chip 100 k pullup resistor. 22 vid2/irq2 digital input. core voltage id readouts from the proce ssor. this value is read into the vid0?vid3 status register. can also be reconfigured as an interrupt input. it has an on ? chip 100 k pullup resistor. 23 vid1/irq1 digital input. core voltage id readouts from the proce ssor. this value is read into the vid0?vid3 status register. can also be reconfigured as an interrupt input. it has an on ? chip 100 k pullup resistor. 24 vid0/irq0 digital input. core voltage id readouts from the proce ssor. this value is read into the vid0?vid3 status register. can also be reconfigured as an interrupt input. it has an on ? chip 100 k pullup resistor.
ADM1024 http://onsemi.com 4 electrical characteristics t a = t min to t max , v cc = v min to v max , unless otherwise noted. (note 1 and 2) parameter test conditions/comments min typ max unit power supply supply voltage, v cc 2.8 3.3 5.5 v supply current, i cc interface inactive, adc active adc inactive, dac active shutdown mode 1.4 1.0 45 3.5 145 ma a temperature ? to ? digital converter internal sensor accuracy 0 c t a 100 c t a = 25 c 3.0 2.0 c resolution 1.0 c external diode sensor accuracy 0 c t a 100 c 25 c 3.0 5.0 c resolution 1.0 c remote sensor source current high level low level 80 4.0 110 6.5 150 9.0 a analog ? to ? digital converter (including mux and attenuators) total unadjusted error (tue) (12 v in ) (note 3) 4.0 % tue (a in , v ccp , 2.5 v in , 5.0 v in ) 3.0 % differential non ? linearity (dnl) 1.0 lsb power supply sensitivity 1.0 %/v conversion time (analog input or internal temperature) (note 4) 754.8 856.8 s conversion time (external temperature) (note 4) 9.6 ms input resistance (2.5 v, 5.0 v, 12 v, v ccp1 , v ccp2 ) 80 140 200 k input resistance (a in1 , a in2 ) 5.0 m analog output output voltage range 0 2.5 v total unadjusted error (tue) i l = 2 ma 3.0 % full ? scale error 1.0 5.0 % zero ? scale error no load 2.0 lsb differential non ? linearity (dnl) monotonic by design 1.0 lsb integral non ? linearity 1.0 lsb output source current 2.0 ma output sink current 1.0 ma fan rpm ? to ? digital converter accuracy 0 c t a 100 c 12 % full ? scale count 255 fan1 to fan2 nominal input rpm (note 5) divisor = 1, fan count = 153 divisor = 2, fan count = 153 divisor = 3, fan count = 153 divisor = 4, fan count = 153 8800 4400 2200 1100 rpm internal clock frequency 0 c t a 100 c 19.8 22.5 25.2 khz digital outputs (ntest_out) output high voltage, v oh i out = +3.0 ma, v cc = 2.85 v ? 3.60 v 2.4 v output low voltage, v ol i out = ? 3.0 ma, v cc = 2.85 v ? 3.60 v 0.4 v open ? drain digital outputs (int , therm , reset ) (note 6) output low voltage, v ol i out = 3.0 ma, v cc = 3.60 v 0.4 v high level output leakage current, i oh v out = v cc 0.1 100 a reset and ci pulsewidth 20 45 ms
ADM1024 http://onsemi.com 5 electrical characteristics t a = t min to t max , v cc = v min to v max , unless otherwise noted. (note 1 and 2) parameter unit max typ min test conditions/comments open ? drain serial databus output (sda) output low voltage, v ol i out = ? 3.0 ma, v cc = 2.85 v ? 3.60 v 0.4 v high level output leakage current, i oh v out = v cc 0.1 100 a serial bus digital inputs (scl, sda) input high voltage, v ih 2.2 v input low voltage, v il 0.8 v hysteresis 500 mv glitch immunity 100 ns digital input logic levels (add, ci, reset , vid0 ? vid4, fan1, fan2) (note 7) input high voltage, v ih v cc = 2.85 v ? 5.5 v 2.2 v input low voltage, v il v cc = 2.85 v ? 5.5 v 0.8 v ntest_in input high current, i ih v cc = 2.85 v ? 5.5 v 2.2 v digital input current input high current, i ih v in = v cc ?1.0 a input low current, i il v in = 0 1.0 a input capacitance, c in 20 pf serial bus timing (note 8) clock frequency, f sclk see figure 2 400 khz glitch immunity, t sw see figure 2 50 ns bus free time, t buf see figure 2 1.3 s start setup time, t su; sta see figure 2 600 ns start hold time, t hd; sta see figure 2 600 ns scl low time, t low see figure 2 1.3 s scl high time, t high see figure 2 0.6 s scl, sda rise time, t r see figure 2 300 ns scl, sda fall time, t f see figure 2 300 s data setup time, t su; dat see figure 2 100 ns data hold time, t hd; dat see figure 2 900 ns 1. all voltages are measured with respect to gnd, unless otherwise specified. 2. typicals are at t a = 25 c and represent the most likely parametric norm. shutdown current typ is measured with v cc = 3.3v. 3. tue (total unadjusted error) includes offset, gain, and linearity errors of the adc, multiplexer, and on ? chip input attenuators, including an external series input protection resistor value between 0 k and 1 k . 4. total monitoring cycle time is nominally m 755 s + n 33244 s, where m is the number of channels configured as analog inputs, plus 2 for the internal v cc measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (d1 and d2). 5. the total fan count is based on two pulses per revolution of the fan tachometer output. 6. open ? drain digital outputs may have an external pullup resistor connected to a voltage lower or higher than v cc (up to 6.5 v absolute maximum). 7. all logic inputs except add are tolerant of 5.0 v logic levels, even if v cc is less than 5.0 v. add is a three ? state input that may be connected to v cc , gnd, or left open ? circuit. 8. timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.2 v for a rising edge. figure 2. serial bus timing diagram p s ps scl sda t r t f t low t hd:sta t hd:dat t high t su:dat t su:sta t hd:sta t su:sto t buf
ADM1024 http://onsemi.com 6 typical performance characteristics figure 3. temperature error vs. pc board track resistance figure 4. temperature error vs. power supply noise frequency figure 5. temperature error vs. common ? mode noise frequency figure 6. pentium iii temperature vs. ADM1024 reading figure 7. temperature error vs. capacitance between d+ and d? figure 8. temperature error vs. differential ? mode noise fre q uenc y measured temperature reading 0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 90 100 110 1 3.3 10 30 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 100 leak resistance (m?) temperature error (c) dxp to gnd dxp to v cc (5.0 v) 50 500 5k 50k ?1 0 1 2 3 4 5 6 50m frequency (hz) temperature error ( c) 500k 5m 250mv p ? p remote 100mv p ? p remote 50 500 5k 50k ?5 0 5 10 15 20 25 50m frequency (hz) temperature error ( c) 500k 5m 100mv p ? p 50mv p ? p 25mv p ? p 1 2.2 3.2 4.7 ?5 0 5 10 15 20 25 10 dxp ? dxn capacitance (nf) temperature error ( c) 7 50 500 5k 50k 0 1 2 3 7 8 10 50m frequency (hz) temperature error ( c) 500k 5m 25m 100k 4 5 6 9 10mv sq. wave
ADM1024 http://onsemi.com 7 typical performance characteristics figure 9. standby current vs. temperature 22.5 23.0 23.5 24.0 26.0 26.5 temperature ( c) standby current ( a) 24.5 25.0 25.5 ?40 ?20 0 20 40 60 80 100 120 v dd = 3.3 v
ADM1024 http://onsemi.com 8 general description the ADM1024 is a complete system hardware monitor for microprocessor ? based systems. the device communicates with the system via a serial smbus. the serial bus controller has a hardwired address line for device selection (pin 1), a serial data line for reading and writing addresses and data (sda, pin 14), and an input line for the serial clock (pin 3), and an input line for the serial clock (pin 4). all control and programming functions of the ADM1024 are performed over the serial bus. measurement inputs programmability of the measurement inputs makes the ADM1024 extremely flexible and versatile. the device has a 10 ? bit adc and nine measurement input pins that can be configured in different ways. pins 5 and 6 can be programmed as general ? purpose analog inputs with a range of 0 v to 2.5 v, or as digital inputs to monitor the speed of fans with digital tachometer outputs. the fan inputs can be programmed to accommodate fans with different speeds and different numbers of pulses per revolution from their tachometer outputs. pins 13 and 14 are dedicated temperature inputs and may be connected to the cathode and anode of an external temperature sensing diode. pins 15, 16, and 19 are dedicated analog inputs with on ? chip attenuators, configured to monitor 12 v, 5.0 v, and the processor core voltage, respectively. pins 17 and 18 may be configured as analog inputs with on ? chip attenuators to monitor a second processor core voltage and a 2.5 v supply, or they may be configured as a temperature input and connected to a second temperature ? sensing diode. the adc also accepts input from an on ? chip band gap temperature sensor that monitors system ? ambient temperature. finally, the ADM1024 monitors the supply from which it is powered, so there is no need for a separate 3.3 v analog input if the chip v cc is 3.3 v. the range of this v cc measurement can be configured for either a 3.3 v or 5.0 v v cc by bit 3 of the channel mode register. sequential measurement when the ADM1024 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. measured values from these inputs are stored in value registers. these can be read out over the serial bus, or can be compared with programmed limits stored in the limit registers. the results of out ? of ? limit comparisons are stored in the interrupt status registers, and will generate an interrupt on the int line (pin 10). any or all of the interrupt status bits can be masked by appropriate programming of the interrupt mask register. processor voltage id five digital inputs (vid4 to vid0?pins 20 to 24) read the processor voltage id code. these inputs can also be reconfigured as interrupt inputs. the vid pins have internal 100 k pullup resistors. chassis intrusion a chassis intrusion input (pin 7) is provided to detect unauthorized tampering with the equipment. reset a reset input/output (pin 12) is provided. pulling this pin low will reset all ADM1024 internal registers to default values. the ADM1024 can also be programmed to give a low going 45 ms reset pulse at this pin. analog output the ADM1024 contains an on ? chip, 8 ? bit dac with an output range of 0 v to 2.5 v (pin 11). this is typically used to implement a temperature ? controlled fan by controlling the speed of a fan dependent upon the temperature measured by the on ? chip temperature sensor. testing of board level connectivity is simplified by providing a nand tree test function. the aout (pin 11) also doubles as a nand test input, while pin 1 doubles as a nand tree output. internal registers of the ADM1024 a brief description of the ADM1024?s principal internal registers follows. more detailed information on the function of each register is given in table 6 to table 19: ? configuration registers: provide control and configuration. ? channel mode register: stores the data for the operating modes of the input channels. ? address pointer register: this register contains the address that selects one of the other internal registers. when writing to the ADM1024, the first byte of data is always a register address, which is written to the address pointer register. ? interrupt (int ) status registers: two registers to provide status of each interrupt event. these registers are also mirrored at addresses 4ch and 4dh. ? interrupt (int ) mask registers: allow masking of individual interrupt sources. ? temperature configuration register: the configuration of the temperature interrupt is controlled by the lower three bits of this register. ? vid/fan divisor register: the status of the vid0 to vid4 pins of the processor can be written to and read from these registers. divisor values for fan speed measurement are also stored in this register.
ADM1024 http://onsemi.com 9 ? value and limit registers: the results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values. ? analog output register: the code controlling the analog output dac is stored in this register. ? chassis intrusion clear register: a signal latched on the chassis intrusion pin can be cleared by writing to this register. serial bus interface control of the ADM1024 is carried out via the serial bus. the ADM1024 is connected to this bus as a slave device, under the control of a master device, e.g., ich. the ADM1024 has a 7 ? bit serial bus address. when the device is powered up, it will do so with a default serial bus address. the 5 msbs of the address are set to 01011, and the 2 lsbs are determined by the logical states of pin 1 (ntest out/add). this is a three ? state input that can be grounded, connected to v cc , or left open ? circuit to give three different addresses. table 1. add pin truth table add pin a1 a0 gnd 1 0 no connect 0 0 v cc 0 1 if add is left open ? circuit, the default address will be 0101100. add is sampled only at powerup, so any changes made while power is on will have no immediate effect. the facility to make hardwired changes to a1 and a0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADM1024 is used in a system. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high ? to ? low transition on the serial data line sda while the serial clock line, scl, remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next eight bits, consisting of a 7 ? bit address (msb first) plus an r/w bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, the master will write to the slave device. if the r/w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low ? to ? high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the case of the ADM1024, write operations contain either one or two bytes, and read o perations contain one byte and perform the following functions. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 10 the device address is sent over the bus followed by r/w set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register, there are two possibilities: 1. if the ADM1024?s address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the ADM1024 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. this is shown in figure 11.
ADM1024 http://onsemi.com 10 a read operation is then performed consisting of the serial bus address, r/w bit set to 1, followed by the data byte read from the data register. this is shown in figure 12. 2. if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so figure 11 can be omitted. figure 10. writing a register address to the address pointer register, then writing data to the selected register 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d0 1 9 scl (continued) sda (continued) ack. by ADM1024 ack. by ADM1024 ack. by ADM1024 start by master stop by master frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte d1 d2 d3 d4 d5 d6 d7 r/w 1 9 91 figure 11. writing to the address pointer register only stop by master d0 1 9 d1 d2 d3 d4 d5 d6 d7 0 scl sda 1 0 1 1 a1 a0 ack. by ADM1024 ack. by ADM1024 start by master frame 1 serial bus address byte frame 2 address pointer register byte r/w 19 figure 12. reading data from a previously selected register stop by master 1 9 scl ack. by ADM1024 start by master frame 1 serial bus address byte 19 r/w 0 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 sda no ack. by master frame 2 data byte from ADM1024 notes 1. although it is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. 2. in figure 10 to figure 12, the serial bus address is shown as the default value 01011(a1)(a0), where a1 and a0 are set by the three ? state add pin. measurement inputs the ADM1024 has nine external measurement pins that can be configured to perform various functions by programming the channel mode register. pins 13 and 14 are dedicated to temperature measurement, while pins 15, 16, and 19 are dedicated analog input channels. their function is unaffected by the channel mode register. pins 5 and 6 can be individually programmed as analog inputs, or as digital fan speed measurement inputs, by programming bits 0 and 1 of the channel mode register. bit 3 of the channel mode register configures the internal v cc measurement range for either 3.3 v or 5.0 v.
ADM1024 http://onsemi.com 11 bits 4 to 6 of the channel mode register enable or disable pins 22 to 24 when they are configured as interrupt inputs by setting bit 7 of the channel mode register. this function is controlled for pins 20 and 21 by bits 6 and 7 of configuration register 2. pins 17 and 18 can be configured as analog inputs or as inputs for external temperature ? sensing diodes by programming bit 2 of the channel mode register. bit 7 of the channel mode register allows the processor core voltage id bits (vid0 to vid4, pins 24 to 20) to be reconfigured as interrupt inputs. a truth table for the channel mode register is given in table 2. table 2. channel mode register (note 1) channel mode register bit controls pin(s) function 0 5 0 = fan1, 1 = a in1 1 6 0 = fan2, 1 = a in2 2 17, 18 0 = 2.5 v, v ccp2 , 1 = d2?, d2+ 3 int. v cc meas. 0 = 3.3 v, 1 = 5.0 v 4 24 0 = vid0, 1 = irq0 5 23 0 = vid1, 1 = irq1 6 22 0 = vid2, 1 = irq2 7 20?24 0 = vid0 to vid4, 1 = interrupt inputs 1. power ? on default = 0000 0000 table 3. a/d output code vs. v in input voltage a/d output +12 v in +5.0 v in v cc (3.3 v) v cc (5.0 v) +2.5 v in +v ccp 1/2 a in (1/2) decimal binary <0.062 <0.026 <0.0172 <0.026 <0.013 <0.014 <0.010 0 00000000 0.062?0.125 0.026?0.052 0.017?0.034 0.026?0.052 0.013?0.026 0.014?0.028 0.010?0.019 1 00000001 0.125?0.188 0.052?0.078 0.034?0.052 0.052?0.078 0.026?0.039 0.028?0.042 0.019?0.029 2 00000010 0.188?0.250 0.078?0.104 0.052?0.069 0.078?0.104 0.039?0.052 0.042?0.056 0.029?0.039 3 00000011 0.250?0.313 0.104?0.130 0.069?0.086 0.104?0.130 0.052?0.065 0.056?0.070 0.039?0.049 4 00000100 0.313?0.375 0.130?0.156 0.086?0.103 0.130?0.156 0.065?0.078 0.070?0.084 0.049?0.058 5 00000101 0.375?0.438 0.156?0.182 0.103?0.120 0.156?0.182 0.078?0.091 0.084?0.098 0.058?0.068 6 00000110 0.438?0.500 0.182?0.208 0.120?0.138 0.182?0.208 0.091?0.104 0.098?0.112 0.068?0.078 7 00000111 0.500?0.563 0.208?0.234 0.138?0.155 0.208?0.234 0.104?0.117 0.112?0.126 0.078?0.087 8 00001000 4.000?4.063 1.666?1.692 1.100?1.117 1.666?1.692 ? ? ? 0.833?0.846 0.900?0.914 0.625?0.635 64 (1/4 ? scale) 01000000 8.000?8.063 3.330?3.560 2.200?2.217 3.330?3.560 ? ? ? 1.667?1.680 1.800?1.814 1.250?1.260 128 (1/2 ? scale) 10000000 12.000?12.063 5.000?5.026 3.300?3.317 5.000?5.026 ? ? ? 2.500?2.513 2.700?2.714 1.875?1.885 192 (3/4 ? scale) 11000000 15.312?15.375 6.380?6.406 4.210?4.230 6.380?6.406 ? ? ? 3.190?3.203 3.445?3.459 2.392?2.402 245 11110101 15.375?15.437 6.406?6.432 4.230?4.245 6.406?6.432 3.203?3.216 3.459?3.473 2.402?2.412 246 11110110 15.437?15.500 6.432?6.458 4.245?4.263 6.432?6.458 3.216?3.229 3.473?3.487 2.412?2.422 247 11110111 15.500?15.563 6.458?6.484 4.263?4.280 6.458?6.484 3.229?3.242 3.487?3.501 2.422?2.431 248 1111 1000 15.563?15.625 6.484?6.510 4.280?4.300 6.484?6.510 3.242?3.255 3.501?3.515 2.431?2.441 249 1111 1001 15.625?15.688 6.510?6.536 4.300?4.314 6.510?6.536 3.255?3.268 3.515?3.529 2.441?2.451 250 1111 1010 15.688?15.750 6.536?6.562 4.314?4.331 6.536?6.562 3.268?3.281 3.529?3.543 2.451?2.460 251 11111011 15.750?15.812 6.562?6.588 4.331?4.348 6.562?6.588 3.281?3.294 3.543?3.558 2.460?2.470 252 11111100 15.812?15.875 6.588?6.615 4.348?4.366 6.588?6.615 3.294?3.307 3.558?3.572 2.470?2.480 253 11111101 a ? to ? d converter these inputs are multiplexed into the on ? chip, successive approximation, analog ? to ? digital converter (adc). this has a resolution of eight bits. the basic input range is 0 v to 2.5 v, which is the input range of ain1 and ain2, but five of the inputs have built ? in attenuators to allow measurement of 2.5 v, 5.0 v, 12 v, and the processor core voltages v ccp1 and v ccp2 without any external components. to allow for the tolerance of these supply voltages, the adc produces an output of 3/4 full scale (decimal 192) for the nominal input
ADM1024 http://onsemi.com 12 voltage, and so has adequate headroom to cope with overvoltages. table 3 shows the input ranges of the analog inputs and output codes of the adc. when the adc is running, it samples and converts an input every 748 s, except for the external temperature (d1 and d2) inputs. these have special input signal conditioning and are averaged over 16 conversions to reduce noise, and a measurement on one of these inputs takes nominally 9.6 ms. input circuits the internal structure for the analog inputs is shown in figure 13. each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first ? order low ? pass filter that gives the input immunity to high frequency noise. figure 13. structure of analog inputs 10pf ain1?ain2 35pf 25pf 25pf (see text) 50pf mux +12v in +5.0v in +2.5v in +v ccp1 /v ccp2 97.3k 42.7k 111.2k 36.7k 55.2k 91.6k 22.7k 122.2k 80k 2.5 v input precautions when using the 2.5 v input, the following precautions should be noted. there is a parasitic diode between pin 18 and v cc due to the presence of a pmos current source (which is used when pin 18 is configured as a temperature input). this will become forward biased if pin 18 is more than 0.3 v above v cc . therefore, v cc should never be powered off with a 2.5 v input connected. setting other input ranges a in1 and a in2 can easily be scaled to voltages other than 2.5 v. if the input voltage range is zero to some positive voltage, all that is required is an input attenuator, as shown in figure 14. figure 14. scaling a in(1 ? 2) v in r1 r2 ain(1?2) negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so it is always positive. (eq. 1) r1 r2 v f s 2.5 2.5 to measure a negative input voltage, an attenuator can be used as shown in figure 15. figure 15. scaling and offsetting a in(1 ? 2) for negative inputs v in r1 ain(1?2) r2 +v os this is a simple and cheap solution, but the following point should be noted. since the input signal is offset but not inverted, the input range is transposed. an increase in the magnitude of the ? 12 v supply (going more negative) will cause the input voltage to fall and give a lower output code from the adc. conversely, a decrease in the magnitude of the ? 12 v supply will cause the adc code to increase. the maximum negative voltage corresponds to zero output from the adc. this means that the upper and lower limits will be transposed. (eq. 2) r1 r2 v f s v os bipolar input ranges can easily be accommodated. by making r1 equal to r2 and v os = 2.5 v, the input range is 2.5 v. other input ranges can be accommodated by adding a third resistor to set the positive full ? scale input voltage. figure 16. scaling and offsetting a in(1 ? 2) for bipolar inputs v in r1 ain(1?2) r2 +v os r3 (r3 has no effect as the input voltage at the device pin is zero when v in = minus full scale.) (eq. 3) r1 r2 v f s r2 (r2 has no effect as the input voltage at the device pin is 2.5 v when v in = plus full scale). r1 r3 v f s 2.5 2.5 (eq. 4) offset voltages other than 2.5 v can be used, but the calculation becomes more complicated. temperature measurement system local temperature measurement the ADM1024 contains an on ? chip band gap temperature sensor, whose output is digitized by the on ? chip adc. the temperature data is stored in the t emperature value register (address 27h) and the lsb from bits 6 and 7 of the temperature configuration register (address 4bh). as both
ADM1024 http://onsemi.com 13 positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in t able 4. theoretically, the temperature sensor and adc can measure temperatures from ? 128 c to +127 c with a resolution of 1 c, although temperatures below ? 40 c and above +125 c are outside the operating temperature range of the device. external temperature measurement the ADM1024 can measure the temperature of two external diode sensors or diode ? connected transistors, connected to pins 13 and 14 or 17 and 18. pins 13 and 14 are a dedicated temperature input channel. pins 17 and 18 can be configured to measure a diode sensor by setting bit 2 of the channel mode register to 1. the forward voltage of a diode or diode ? connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about ?2 mv/ c. unfortunately, the absolute value of v be varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. the technique used in the ADM1024 is to measure the change in v be when the device is operated at two different currents. this is given by: (eq. 5) v be kt q ln ( n ) where: k is boltzmann?s constant. q is the charge on the carrier. t is the absolute temperature in kelvins. n is the ratio of the two currents. figure 17 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. i d+ lpf n i i bias v dd bias diode d? low ? pass filter f c = 65khz v out+ v out? to adc remote sensing transistor figure 17. signal conditioning for external diode temperature sensors if a discrete transistor is used, the collector will not be grounded and should be linked to the base. if a pnp transistor is used, the base is connected to the d ? input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d ? input and the base to the d+ input. to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the d ? input. as the sensor is operating in a noisy environment, c1 is provided as a noise filter. see the layout considerations section for more information on c1. to measure v be , the sensor is switched between operating currents of i and n i. the resulting waveform is passed through a 65 khz low ? pass filter to remove noise, then to a chopper ? stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to v be . this voltage is measured by the adc to give a temperature output in 8 ? bit twos complement format. to further reduce the ef fects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. an external temperature measurement takes nominally 9.6 ms. the results of external temperature measurements are stored in 8 ? bit, twos complement format, as illustrated in table 4. table 4. temperature data format temperature digital output ? 128 c 1000 0000 ? 125 c 1000 0011 ? 100 c 1001 1100 ? 75 c 1011 0101 ? 50 c 1100 1110 ? 25 c 1110 0111 0 c 0000 0000 +0.5 c 0000 0000 +10 c 0000 1010 +25 c 0001 1001 +50 c 0011 0010 +75 c 0100 1011 +100 c 0110 0100 +125 c 0111 1101 +127 c 0111 1111 layout considerations digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the ADM1024 as close as possible to the remote sensing diode. provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided, this distance can be 4 inches to 8 inches. 2. route the d+ and d ? tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible.
ADM1024 http://onsemi.com 14 3. use wide tracks to minimize inductance and reduce noise pickup. a 10 mil track minimum width and spacing is recommended. figure 18. arrangement of signal tracks 10mil gnd d+ gnd d? 10mil 10mil 10mil 10mil 10mil 10mil 10mil 10mil 10mil 10mil 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d? path and at the same temperature. thermocouple effects should not be a major problem as 1 c corresponds to about 240 v, and thermocouple voltages are about 3 v/ c of temperature difference. unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mv. 5. place 0.1 f bypass and 2200 pf input filter capacitors close to the ADM1024. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this will work up to about 6 feet to 12 feet. 7. for really long distances (up to 100 feet) use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d? and the shield to gnd close to the ADM1024. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor may be reduced or removed. cable resistance can also introduce errors. a 1 series resistance introduces about 0.5 c error. limit values limit values for analog measurements are stored in the appropriate limit registers. in the case of voltage measurements, high and low limits can be stored so that an interrupt request will be generated if the measured value goes above or below acceptable values. in the case of temperature, a hot temperature or high limit can be programmed, and a hot temperature hysteresis or low limit, which will usually be some degrees lower. this can be useful as it allows the system to be shut down when the hot limit is exceeded, and restarted automatically when it has cooled down to a safe temperature. monitoring cycle time the monitoring cycle begins when a 1 is written to the start bit (bit 0), and a 0 to the int _clear bit (bit 3) of the configuration register. int _enable (bit 1) should be set to 1 to enable the int output. the adc measures each analog input in turn; as each measurement is completed, the result is automatically stored in the appropriate value register. this ?round robin? monitoring cycle continues until it is disabled by writing a 0 to bit 0 of the configuration register. as the adc will normally be left to free ? run in this manner, the time taken to monitor all the analog inputs will normally not be of interest, as the most recently measured value of any input can be read out at any time. for applications where the monitoring cycle time is important, it can be calculated as follows: (eq. 6) m t 1 n t 2 where: m ? the number of inputs configured as analog inputs, plus the internal v cc measurement and internal temperature sensor. t 1 ? the time taken for an analog input conversion, nominally 6.044 ms. n ? the number of inputs configured as external temperature inputs. t 2 ? the time taken for a temperature conversion, nominally 33.24 ms. this rapid sampling of the analog inputs ensures a quick response in the event of any input going out of limits, unlike other monitoring chips that employ slower adcs. fan monitoring cycle time when a monitoring cycle is started, monitoring of the fan speed inputs begins at the same time as monitoring of the analog inputs. however, the two monitoring cycles are not synchronized in any way. the monitoring cycle time for the fan inputs is dependent on fan speed and is much slower than for the analog inputs. for more details, see the fan speed measurement section. input safety scaling of the analog inputs is performed on ? chip, so external attenuators are normally not required. however, since the power supply voltages will appear directly at the pins, it is advisable to add small external resistors in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. as the resistors will form part of the input attenuators, they will affect the accuracy of the analog measurement if their value is too high. the analog input channels are calibrated assuming an external series resistor of 500 , and the accuracy will remain within specification for any value from 0 k to 1 k , so a standard 510 resistor is suitable. the worst such accident would be connecting ? 2.0 v to +12 v, a total of 24 v difference. with the series resistors, this would draw a maximum current of approximately 24 ma.
ADM1024 http://onsemi.com 15 analog output the ADM1024 has a single analog output from an unsigned 8 ? bit dac that produces 0 v to 2.5 v. the analog output register defaults to ff during power ? on reset, which produces maximum fan speed. the analog output may be amplified and buf fered with external circuitry such as an op amp and transistor to provide fan speed control. suitable fan drive circuits are given in figure 19 to figure 24. when using any of these circuits, the following points should be noted: 1. all of these circuits will provide an output range from 0 v to almost 12 v, apart from figure 25 which loses the base ? emitter voltage drop of q1 due to the emitter ? follower configuration. 2. to amplify the 2.5 v range of the analog output up to 12 v, the gain of these circuits needs to be around 4.8. 3. care must be taken when choosing the op amp to ensure that its input common ? mode range and output voltage swing are suitable. 4. the op amp may be powered from the 12 v rail alone or from 12 v. if it is powered from 12 v, then the input common ? mode range should include ground to accommodate the minimum output voltage of the dac, and the output voltage should swing below 0.6 v to ensure that the transistor can be turned fully off. 5. if the op amp is powered from ? 12 v, precautions such as a clamp diode to ground may be needed to prevent the base ? emitter junction of the output transistor being reverse ? biased in the unlikely event that the output of the op amp should swing negative for any reason. figure 19. fan drive circuit with op amp and emitter ? follower aout 12v q1 2n2219a 1/4 lm324 r1 10k? r2 36k? figure 20. fan drive circuit with op amp and pnp transistor aout 12v q1 bd136 2sa968 1/4 lm324 r1 10k? r3 1k? r2 39k? r4 1k? figure 21. fan driver circuit with op amp and p ? channel mosfet aout 12v q1 irf9620 1/4 lm324 r1 10k? r3 100k? r2 39k? figure 22. discrete fan drive circuit with p ? channel mosfet, single supply aout 12v q3 irf9620 r2 100k? r3 3.9k? r4 1k? r1 100k? q1/q2 mbt3904 dual figure 23. discrete fan drive circuit with p ? channel mosfet, dual supply aout 12v q3 irf9620 r2 100k? ?12v q1/q2 mtb3904 dual r3 39k? r4 10k? r1 4.7k? figure 24. discrete fan drive circuit with bipolar output, dual supply aout 12v r2 100k? q4 bd132 tip32a q3 bc556 2n3906 q1/q2 mbt3904 dual r1 100k? r3 3.9k? r4 1k? r5 100k?
ADM1024 http://onsemi.com 16 6. in all these circuits, the output transistor must have an i cmax greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when the fan is not operating at full speed. 7. if the fan motor produces a large back emf when switched off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes very quickly from full scale to zero. fault ? tolerant fan control the ADM1024 incorporates a fault ? tolerant fan control capability that can override the setting of the analog output and force it to maximum to give full fan speed in the event of a critical overtemperature problem even if, for some reason, this has not been handled by the system software. there are four temperature set points that will force the analog output to ffh if any one of them is exceeded for three or more consecutive measurements. two of these limits are programmable by the user and two are hardware limits intended as must not exceed limits that cannot be changed. the analog output will be forced to ffh if: the temperature measured by the on ? chip sensor exceeds the limit programmed into register address 13hp; or: the temperature measured by either of the remote sensors exceeds the limit programmed into address 14h; or: the temperature measured by the on ? chip sensor exceeds 70 c, which is hardware programmed into a read ? only register at address 17h; or: the temperature measured by either of the remote sensors exceeds 85 c, which is hardware programmed into a read ? only register at address 18h. once the hardware override of the analog output is triggered, it will return to normal operation only after three consecutive measurements that are 5 degrees lower than each of the above limits. the analog output can also be forced to ffh by pulling the therm pin (pin 2) low. the limits in registers 13h and 14h can be programmed by the user. obviously, these limits should not exceed the hardware values in registers 17h and 18h, as they would have no effect. the power ? on default values of these registers are the same as the two hardware registers, 70 c and 85 c, respectively, so there is no need to program them if these limits are acceptable. once these registers have been programmed, or if the defaults are acceptable, the values in these registers can be locked by writing a 1 to bits 1 and 2 of configuration register 2 (address 4ah). this prevents any unauthorized tampering with the limits. these lock bits can only be written to 1 and can only be cleared by power ? on reset or by taking the reset pin low, so registers 13h and 14h cannot be written to again unless the device is powered off, then on. layout and grounding analog inputs will provide best accuracy when referred to a clean ground. a separate, low impedance ground plane for analog ground, which provides a ground point for the voltage dividers and analog components, will provide best performance but is not mandatory. the power supply bypass, the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as possible to the ADM1024. fan inputs pins 5 and 6 may be configured as analog inputs or fan speed inputs by programming bits 0 and 1 of the channel mode register. the power ? on default for these bits is all zeros, which makes pins 5 and 6 fan inputs. signal conditioning in the ADM1024 accommodates the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 to v cc . in the event that these inputs are supplied from fan outputs that exceed 0 v to 6.5 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 25 to figure 28 show circuits for most common fan tachometer outputs. if the fan tachometer output has a resistive pullup to v cc , it can be directly connected to the fan input, as shown in figure 25. figure 25. fan with tach pullup to +v cc 160k pullup 4.7k typ 12v v cc fan speed counter fan1 or fan2 tach output if the fan output has a resistive pullup to 12 v (or other voltage greater than 6.5 v), the fan output can be clamped with a zener diode, as shown in figure 26. the zener voltage should be chosen so it is greater than v ih but less than 6.5 v, allowing for the voltage tolerance of the zener. a value of between 3.0 v and 5.0 v is suitable. figure 26. fan with tach. pullup to voltage >6.5 v ( e. g ., 12 v ) clam p ed with zener diode * choose zd1 voltage approximately 0.8 v cc . 12v v cc fan speed counter fan1 or fan2 tach output zd1 * zener 160k pullup 4.7k typ
ADM1024 http://onsemi.com 17 if the fan has a strong pullup (less than 1 k ) to 12 v, or a totem ? pole output, then a series resistor can be added to limit the zener current, as shown in figure 27. alternatively, a resistive attenuator may be used, as shown in figure 28. r1 and r2 should be chosen such that: (eq. 7) 2.0 v
v pullup r2 r pullup r1 r2
5.0 v the fan inputs have an input resistance of nominally 160 k to ground, so this should be taken into account when calculating resistor values. with a pullup voltage of 12 v and pullup resistor less than 1 k , suitable values for r1 and r2 would be 100 k and 47 k . this will give a high input voltage of 3.83 v. figure 27. fan with strong tach pullup to >v cc or totem pole output, clamped with zener and resistor * choose zd1 voltage approximately 0.8 v cc pullup totem ? pole 12v v cc fan speed counter fan1 or fan2 tach output zd1 * zener 160k typ <1k or r1 10k figure 28. fan with strong tach pullup to > v cc or totem pole output, attenuated with r1/r2 * see text. 12v v cc fan speed counter fan1 or fan2 tach output r1 * r2 * 160k <1k fan speed measurement the fan counter does not count the fan tachometer output pulses directly because the fan speed may be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on ? chip 22.5 khz oscillator into the input of an 8 ? bit counter for two periods of the fan tachometer output, as shown in figure 29; the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. figure 29. fan speed measurement 22.5khz clock cycle period start of monitoring measurement fan1 period measurement fan2 input fan1 input fan2 reg. 1 bit 0 config. the monitoring cycle begins when a one is written to the start bit (bit 0), and a zero to the int _clear bit (bit 3) of the configuration register. int _enable (bit 1) should be set to one to enable the int output. the measurement begins on the rising edge of a fan tachometer pulse, and ends on the next ? butone rising edge. the fans are monitored sequentially, so if only one fan is monitored, the monitoring time is the time taken after the start bit for it to produce two complete tachometer cycles or for the counter to reach full scale, whichever occurs sooner. if more than one fan is monitored, the monitoring time depends on the speed of the fans and the timing relationship of their tachometer pulses. this is illustrated in figure 30. once the fan speeds have been measured, they will be stored in the fan speed value registers and the most recent value can be read at any time. the measurements will be updated as long as the monitoring cycle continues. to accommodate fans of different speed and/or different numbers of output pulses per revolution, a prescaler (divisor) of 1, 2, 4, or 8 may be added before the counter. the default value is 2, which gives a count of 153 for a fan running at 4400 rpm, producing two output pulses per revolution. the count is calculated by the equation: (eq. 8) count 22.5 10 3 60 rpm divisor for constant speed fans, fan failure is normally considered to have occurred when the speed drops below 70% of nominal, which would correspond to a count of 219. full scale (255) would be reached if the fan speed fell to 60% of its nominal value. for temperature ? controlled variable speed fans, the situation will be different. table 5 shows the relationship between fan speed and time per revolution at 60%, 70%, and 100% of nominal rpm for fan speeds of 1100, 2200, 4400, and 8800 rpm, and the divisor that would be used for each of these fans, based on two tachometer pulses per revolution. fan1 and f an2 divisors are programmed into bits 4 to 7 of the vid0?3/fan divisor register.
ADM1024 http://onsemi.com 18 table 5. fan speeds and divisors time per divisor rpm nominal rpm rev (ms) 70% rpm rev 70% (ms) 60% rpm rev 60% (ms) 1 8800 6.82 6160 9.74 5280 11.36 2 4400 13.64 3080 19.48 2640 22.73 4 2200 27.27 1540 38.96 1320 45.44 8 1100 54.54 770 77.92 660 90.90 limit values fans in general will not over ? speed if run from the correct voltage, so the failure condition of interest is under ? speed due to electrical or mechanical failure. for this reason only, low speed limits are programmed into the limit registers for the fans. it should be noted that, since fan period rather than speed is being measured, a fan failure interrupt will occur when the measurement exceeds the limit value. monitoring cycle time the monitoring cycle time depends on the fan speed and number of tachometer output pulses per revolution. two complete periods of the fan tachometer output (three rising edges) are required for each fan measurement. therefore, if the start of a fan measurement just misses a rising edge, the measurement can take almost three tachometer periods. in order to read a valid result from the fan value registers, the total monitoring time allowed after starting the monitoring cycle should, therefore, be three tachometer periods of fan1 plus three tachometer periods of fan2 at the lowest normal fan speed. although the fan monitoring cycle and the analog input monitoring cycle are started together, they are not synchronized in any other way. fan manufacturers manufacturers of cooling fans with tachometer outputs are listed below: nmb tech 9730 independence ave. chatsworth, california 91311 phone: 818 ? 341 ? 3355; fax: 818 ? 341 ? 8207 model frame size airflow cfm 2408nl 2.36 in sq 0.79 in; (60 mm sq 20 mm) 9?16 2410ml 2.36 in sq 0.98 in; (60 mm sq 25 mm) 14?25 3108nl 3.15 in sq 0.79 in; (80 mm sq 20 mm) 25?42 3110kl 3.15 in sq 0.98 in; (80 mm sq 25 mm) 25?40 mechatronics inc. p.o. box 613 preston, wa 98050 800 ? 453 ? 4569 models?various sizes available with tachometer output option. sanyo denki, america, inc. 468 amapola avenue torrance, ca 90501 310 ? 783 ? 5400 models?109p series chassis intrusion input the chassis intrusion input is an active high input/open ? drain output intended for detection and signalling of unauthorized tampering with the system. an external circuit powered from the system?s cmos backup battery is used to detect and latch a chassis intrusion event, whether or not the system is powered up. once a chassis intrusion has been detected and latched, the ci input will generate an interrupt when the system is powered up. the actual detection of chassis intrusion is performed by an external circuit that will, for example, detect when the cover has been removed. a wide variety of techniques may be used for the detection, for example: ? microswitch that opens or closes when the cover is removed. ? reed switch operated by magnet fixed to the cover. ? hall ? effect switch operated by magnet fixed to the cover. ? phototransistor that detects light when the cover is removed. the chassis intrusion interrupt will remain asserted until the external detection circuit is reset. this can be achieved by setting bit 7 of the chassis intrusion clear register to one, which will cause the ci pin to be pulled low for at least 20 ms. this register bit is self ? clearing. the chassis intrusion circuit should be designed so that it can be reset by pulling its output low. a suitable chassis intrusion circuit using a photo ? transistor is shown in figure 30. light falling on the photo ? transistor when the pc cover is removed will cause it to turn on and pull up the input of 1, thus setting the latch n3/n4. after the cover is replaced, a low reset on the ci output will pull down the input of n4, resetting the latch. figure 30. chassis intrusion detector and latch 74hc132 ci mrd901 1n914 5.0 v 1n914 n1 n2 n3 n4 cmos backup battery 1 2 3 4 5 6 7 14 13 12 11 10 9 8 470k 100k 10k
ADM1024 http://onsemi.com 19 the chassis intrusion input can also be used for other types of alarm input. figure 31 shows a temperature alarm circuit using an ad22105 temperature switch sensor. this produces a low going output when the preset temperature is exceeded, so the output is inverted by q1 to make it compatible with the ci input. q1 can be almost any small ? signal npn transistor, or a ttl or cmos inverter gate may be used if one is available. see the ad22105 data sheet for information on selecting r set . figure 31. using the ci input with a temperature sensor ci q1 ad22105 temperature sensor r set v cc 6 3 2 1 7 r1 10k? note: the chassis intrusion input does not have a protective clamp diode to v cc , as this could pull down the chassis intrusion latch and reset it when the ADM1024 is powered down. the ADM1024 interrupt structure the interrupt structure of the ADM1024 is shown in figure 32. as each measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. the result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of the interrupt status registers via a data demultiplexer and used to set that bit high or low as appropriate. the interrupt mask registers have bits corresponding to each of the interrupt status register bits. setting an interrupt mask bit high forces the corresponding status bit output low, while setting an interrupt mask bit low allows the corresponding status bit to be asserted. after masking, the status bits are all or?d together to produce the int output, which will pull low if any unmasked status bit goes high, i.e., when any measured value goes out of limit. the ADM1024 also has a dedicated output for temperature interrupts only, the therm input/output pin 2. the function of this is described later. the int output is enabled when bit 1 of configuration register 1 (int _enable) is high, and bit 3 (int _clear) is low. the int pin has an internal, 100 k pullup resistor. vid/irq inputs the processor voltage id inputs vid0 to vid4 can be reconfigured as interrupt inputs by setting bit 7 of the channel mode register (address 16h). in this mode they operate as level ? triggered interrupt inputs, with vid0/irq0 to vid2/irq2 being active low and vid3/irq3 and vid4/irq4 being active high. the individual interrupt inputs can be enabled or masked by setting or clearing bits 4 to 6 of the channel mode register and bits 6 and 7 of configuration register 2 (address 4ah). these interrupt inputs are not latched in the ADM1024, so they do not require clearing as do bits in the status registers. however, the external interrupt source should be cleared once the interrupt has been services, or the interrupt request will be reasserted. interrupt clearing reading an interrupt status register will output the contents of th e register, then clear it. it will remain cleared until the monitoring cycle updates it, so the next read operation should not be performed on the register until this has happened, or the result will be invalid. the time taken for a complete monitoring cycle is mainly dependent on the time taken to measure the fan speeds, as described earlier. the int output is cleared with the int _clear bit, which is bit 3 of the configuration register, without affecting the contents of the interrupt (int) status registers. interrupt status mirror registers whenever a bit in one of the interrupt status registers is updated, the same bit is written to duplicate registers at addresses 4ch and 42h. these registers allow a second management system to access the status data without worrying about clearing the data. the data in these registers is for reading only and has no effect on the interrupt output.
ADM1024 http://onsemi.com 20 figure 32. interrupt register structure int 16 mask bits value 4 5 6 7 vid4/irq4 6 7 therm therm vid0?vid4 registers channel mode register configuration register 2 from value and limit registers high limit 1 = out data demultiplexer int. temp ext. temp1 fan1/ain1 fan2/ain2 reserved reserved ci d1 fault d2 fault 2.5v/ext. temp 2 v ccp1 v cc +5.0v in +12v in v ccp2 masking data from bus interrupt mask registers 1 and 2 (same bit order as status registers) mask gating 11 status bit mask bit int_enable int_clear configuration register 1 therm clear therm 0 1 2 3 4 5 6 7 interrupt status register 2 0 1 2 3 4 5 6 7 interrupt status register 1 high and low limit comparators low limit of limit vid2/irq2 vid3/irq3 vid0/irq0 vid1/irq1 temperature interrupt modes the ADM1024 has two distinct methods of producing interrupts for out ? of ? limit temperature measurements from the internal or external sensors. temperature errors can generate an interrupt on the int pin along with other interrupts, but there is also a separate therm pin that generates an interrupt only for temperature errors. operation of the int output for temperature interrupts is illustrated in figure 33 assuming that the temperature starts off within the programmed limits and that temperature interrupt sources are not masked, int will go low if the temperature measured by any of the internal or external sensors exceeds the programmed high temperature limit for that sensor, or the hardware limits in register 13h, 14h, 17h, or 18h. figure 33. operation of int for temperature interrupts temp high limit low limit int 1 1 1 1 1 1 100 c 90 c 80 c 70 c 60 c 50 c 40 c acpi control methods clear event 1 acpi and default control methods adjust temperature limit values.
ADM1024 http://onsemi.com 21 once the interrupt has been cleared, it will not be reasserted even if the temperature remains above the high limit(s). however, int will be reasserted if: the temperature falls below the low limit for the sensor; or: the high limit(s) is/are reprogrammed to a new value, and the temperature then rises above the new high limit on the next monitoring cycle; or: the therm pin is pulled low externally, which sets bit 5 of interrupt status register 2; or: an interrupt is generated by another source. similarly, should the temperature measured by a sensor start off within limits then fall below the low limit, int will be asserted. once cleared, it will not be reasserted unless: the temperature rises above the high limit; or: the low limit(s) is/are reprogrammed, and the temperature then falls below the new low limit; or: the therm pin is pulled low externally, which sets bit 5 of interrupt status register 2; or: an interrupt is generated by another source. therm input/output the thermal management input/output (therm ) is a logic input/output with an internal, 100 k pullup resistor, that provides a separate output for temperature interrupts only. it is enabled by setting bit 2 of configuration register 1. the therm output has two operating modes that can be programmed by bit 3 of confi guration register 2 (address 4ah). with this bit set to the default value of 0, the therm output operates in ?default? interrupt mode. with this bit set to 1, the therm output operates in ?acpi? mode. thermal interrupts can still be generated at the int output while therm is enabled, but if these are not required they can be masked by writing a 1 to bit 0 of configuration register 2 (address 4ah). the therm pin can also function as a logic input for an external sensor, for example, a temperature sensor such as the adm22105 used in figure 35. if therm is taken low by an external source, the analog output will be forced to ffh to switch a controlled fan to maximum speed. this also generates an int output as previously described. default mode in default mode, the therm output operates like a thermostat with hysteresis. therm will go low and bit 5 of interrupt status register 2 will be set, if the temperature measured by any of the sensors exceeds the high limit programmed for that sensor. it will remain asserted until reset by reading interrupt status register 2, by setting bit 6 of configuration register 1, or when the temperature falls below the low limit programmed for that sensor. figure 34. int or therm output in default mode temp temp high limit temp low limit therm cleared by read or therm clear programmed value analog output cleared by temp falling below low limit 0xff ext therm input if therm is cleared by reading the status register, it will be reasserted after the next temperature reading and comparison if it remains above the high limit. if therm is cleared by setting bit 6 of configuration register 1, it cannot be reasserted until this bit is cleared. therm will also be asserted if one of the hardware temperature limits at addresses 13h, 14h, 17h, or 18h is exceeded for three consecutive measurements. when this happens, the analog output will be forced to ffh to boost a controlled cooling fan to full speed. reading status register 1 will not clear therm in this case, because errors caused by exceeding the hardware temperature limits are stored in a separate register that is not cleared by reading the status register. in this case, therm can only be cleared by setting bit 0 of configuration register 2. therm will be cleared automatically if the temperature falls at least 5 degrees below the limit for three consecutive measurements. acpi mode in acpi mode, therm responds only to the hardware temperature limits at addresses 13h, 14h, 17h, and 18h, not to the software ? programmed limits. figure 35. therm output in acpi mode temp hardware trip point therm analog output programmed value 5 0xff 0xff therm ext input therm will go low if either the internal or external hardware temperature limit is exceeded for three consecutive measurements. it will remain low until the temperature falls at least 5 degrees below the limit for three consecutive measurements. while therm is low, the analog output will go to ffh to boost a controlled fan to full speed.
ADM1024 http://onsemi.com 22 reset input/output reset (pin 12) is an i/o pin that can function as an open ? drain output, providing a low going 20 ms output pulse when bit 4 of the configuration register is set to 1, provided the reset function has first b een enabled by setting bit 7 of interrupt mask registers 2 to 1. the bit is automatically cleared when the reset pulse is output. pin 11 can also function as a reset input by pulling this pin low to reset the internal registers of the ADM1024 to default values. only those registers that have power ? on default values as listed in table 6 are affected by this function. the dac, value, and limit registers are not affected. nand tree tests a nand gate is provided in the ADM1024 for automated test equipment (ate) board level connectivity testing. the device is placed into nand test mode by powering up with pin 11 held high. this pin is automatically sampled after powerup; if it is connected high, then the nand test mode is invoked. in nand test mode, all digital inputs may be tested as illustrated below. ntest_out/add will become the nand test output pin. to perform a nand tree test, all pins included in the nand tree should first be driven high. each pin can then be toggled and a resulting toggle can be observed on ntest_out/add. allow for a typical propagation delay of 500 ns. the structure of the nand tree is shown in figure 36. figure 36. nand tree latch c q d enable sda scl vid4 power ? on reset ntest_in/aout ntest_out/add vid0 vid1 vid2 vid3 fan1 fan2 note that ntest_out/add is a dual function line and if both functions are required, then this line should not be hardwired directly to vcc/gnd. instead it should be connected via a 5 k resistor. note: if any of the inputs shown in figure 36 are unused, they should not be connected directly to ground, but via a resistor such as 10 k . this will allow the automatic test equipment (ate) to drive every input high so that the nand tree test can be carried out properly. using the ADM1024 power ? on reset when power is first applie d, the ADM1024 performs a power ? on reset on several of its registers. registers whose power ? on values are not shown have power ? on conditions that are indeterminate (this includes the value and limit registers). the adc is inactive. in most applications, usually the first action after power ? on would be to write limits into the limit registers. power ? on reset clears or initializes the following registers (the initialized values are shown in table 8): ? configuration registers 1 and 2 ? channel mode register ? interrupt (int ) status registers 1 and 2 ? interrupt (int ) status mirror registers 1 and 2 ? interrupt (int ) mask registers 1 and 2 ? vid/fan divisor register ? vid4 register ? chassis intrusion clear register ? test register ? analog output register ? hardware trip registers initialization configuration register initialization performs a similar, but not identical, function to power ? on reset. the test register and analog output register are not initialized. configuration register initialization is accomplished by setting bit 7 of the configuration register high. this bit automatically clears after being set. using the configuration registers control of the ADM1024 is provided through two configuration registers. the adc is stopped upon powerup, and the int _clear signal is asserted, clearing the int output. the configuration registers are used to start and stop the ADM1024; enable or disable interrupt outputs and modes, and provide the initialization function described above. bit 0 of configuration register 1 controls the monitoring loop of the ADM1024. setting bit 0 low stops the monitoring loop and puts the ADM1024 into a low power mode thereby reducing power consumption. serial bus communication is still possible with any register in the ADM1024 while in low power mode. setting bit 0 high starts the monitoring loop. bit 1 of configuration register 1 enables or disables the int interrupt output. setting bit 1 high enables the int output; setting bit 1 low disables the output. bit 2 of configuration register 1 enables or disables the therm output. setting bit 1 high enables the int output; setting bit 1 low disables the output. bit 3 of configuration register 1 is used to clear the int interrupt output when set high. the ADM1024 monitoring function will stop until bit 3 is set low. interrupt status register contents will not be affected. bit 4 of configuration register 1 causes a low going 45 ms (typ) pulse at the reset pin (pin 12). bit 6 of configuration register 1 is used to clear an interrupt at the therm output when it is set to 1. bit 7 of configuration register 1 is used to start a configuration register initialization when it is set to 1. bit 0 of configuration register 2 is used to mask temperature interrupts at the int output when it is set to 1. the therm output is unaffected by this bit.
ADM1024 http://onsemi.com 23 bits 1 and 2 of configuration register 2 lock the values stored in the local and remote fan control registers at addresses 13h and 14h. the values in these registers cannot be changed until a power ? on reset is performed. bit 3 of configuration register 2 selects the therm interrupt mode. the default value of 0 selects one ? time mode. setting this bit to 1 selects acpi mode. starting conversion the monitoring function (analog inputs, temperature, and fan speeds) in the ADM1024 is started by writing to configuration register 1 and setting start (bit 0) high. the int _enable (bit 1) should be set to 1, and int clear (bit 3) set to 0 to enable interrupts. the therm enable bit (bit 2) should be set to 1 and the therm clear bit (bit 6) should be set to 0 to enable temperature interrupts at the therm pin. apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronized in any way. the time taken to complete the analog measurements depends on how they are configured, as described elsewhere. the time taken to complete the fan speed measurements depends on the fan speed and the number of tachometer output pulses per revolution. once the measurements have been completed, the results can be read from the value registers at any time. reduced power and shutdown mode the ADM1024 can be placed in a low power mode by setting bit 0 of the configuration register to 0. this disables the internal adc. full shutdown mode may then be achieved by setting bit 0 of the t est register to 1. this turns off the analog output and stops the monitoring cycle, if running, but does not affect the condition of any of the registers. the device will return to its previous state when this bit is reset to 0. application circuit figure 37 shows a generic application circuit using the ADM1024. the analog monitoring inputs are connected to the power supplies including two processor core voltage inputs. the vid inputs are connected to the processor voltage id pins. there are two tachometer inputs from fans, and the analog output is used to control the speed of a third fan. an opto ? sensor for chassis intrusion detection is connected to the ci input. of course, in an actual application, every input and output may not be used, in which case unused analog and digital inputs should be tied to analog or digital ground as appropriate. figure 37. application circuit ADM1024 + 5.0 v scl sda serial bus vid0/irq0 vid1/irq1 vid2/irq2 vid3/irq3 vid4/irq4 d1+ 12 v 5.0 v 5.0 v fan1/ain1 fan2/ain2 ci gnd d 74hc132 mrd901 1n914 5.0 v 1n914 n1 n2 n3 n4 cmos backup battery 1 2 3 4 5 6 7 14 13 12 11 10 9 8 12 v 2n2219a op295 ntest_in/aout therm therm i/o to other circuits ntest_out/add 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 0.1 f 10 f v cc v cc reset int int to processor d1? +v ccp1 +2.5v in /d2+ +v ccp2 /d2? +5.0v in +12v in transistor sensing temp. processor pins of from vid 510k 510k 510k 510k 510k 100k 470k 10k 10k 10k 39k
ADM1024 http://onsemi.com 24 adm registers table 6. address pointer register bit name r/w description 7?0 address pointer w address of ADM1024 registers. see the following tables for details. table 7. list of registers hex addr description power ? on value (binary bit 7 ? 0) notes 13h internal temperature hardware trip point = 70 c can be written only if the write once bit in configuration register 2 has not been set. values higher than 70 c will have no affect as the fixed trip point in register 16h will be reached first. 14h external temperature hardware trip point = 85 c can be written only if the write once bit in configuration register 2 has not been set. values higher than 85 c will have no affect as the fixed trip point in register 17h will be reached first. 15h test register 0000 00x0 setting bit 0 of this register to 1 selects shutdown mode. caution: do not write to any other bits in this register. 16h channel mode register 0000 0000 this register configures the i nput channels and configures vid0 to vid4 as processor voltage id or interrupt inputs. 17h internal temperature fixed hardware trip point = 70 c read only. cannot be changed. 18h external temperature fixed hardware trip point = 85 c read only. cannot be changed. 19h programmed value of analog output 1111 1111 1ah a in1 low limit indeterminate 1bh a in2 low limit indeterminate 20h 2.5 v measured value/ext. temp2 indeterminate read only 21h v ccp1 measured value indeterminate read only 22h v cc measured value indeterminate read only 23h 5.0 v value indeterminate read only 24h 12 v measured value indeterminate read only 25h v ccp2 measured value indeterminate read only 26h ext. temp1 value indeterminate read only. stores the measurement from a diode sensor connected to pins 13 and 14. 27h internal temperature value indeterminate read only. this register is used to store eight bits of the internal temperature reading. 28h fan1/a in1 value indeterminate read only. stores fan1 or ain1 reading, depending on the configuration of pin 5. 29h fan2/a in1 value indeterminate read only. stores fan2 or ain2 reading, depending on the configuration of pin 6. 2ah reserved indeterminate 2bh 2.5 v/ext. temp2 high limit indeterminate stores high limit for 2.5 v input or, in temperature mode, this register stores the high limit for a diode sensor connected to pins 17 and 18. 2ch 2.5 v/ext. temp2 low limit indeterminate stores low limit for 2.5 v input or, in temperature mode, this register stores the low limit for a diode sensor connected to pins 17 and 18. 2dh v ccp1 high limit indeterminate 2eh v ccp1 low limit indeterminate 2fh v cc high limit indeterminate 30h v cc low limit indeterminate 31h 5.0 v high limit indeterminate 32h 5.0 v low limit indeterminate 33h 12 v high limit indeterminate 34h 12 v low limit indeterminate
ADM1024 http://onsemi.com 25 hex addr notes power ? on value (binary bit 7 ? 0) description 35h v ccp2 high limit indeterminate 36h v ccp2 low limit indeterminate 37h ext. temp1 high limit indeterminate stores high limit for a diode sensor connected to pins 13 and 14. 38h ext. temp1 low limit indeterminate stores low limit for a diode sensor connected to pins 13 and 14. 39h internal temp. high limit indeterminate stores the high limit for the internal temperature reading. 3ah internal temp. low limit indeterminate stores the low limit for the internal temperature reading. 3bh a in1 /fan1 high limit indeterminate stores high limit for ain1 or fan1, depending on the configuration of pin 5. 3ch a in2 /fan2 high limit indeterminate stores high limit for ain2 or fan2, depending on the configuration of pin 6. 3dh reserved indeterminate 3eh company id number 0100 0001 this location will contain the company identification number (read only). 3fh revision number 0001 nnnn last four bits of this location will contain the revision number of the part (read only). 40h configuration register 1 0000 1000 see table 10 41h interrupt int status register 1 0000 0000 see table 11 42h interrupt int status register 2 0000 0000 see table 12 43h int mask register 1 0000 0000 see table 13 44h int mask register 2 0000 0000 see table 14 46h chassis intrusion clear register 0000 0000 see table 15 47h vid0?3/fan divisor register 0101 (vid3?vid0) see table 16 49h vid4 register 1000 000 (vid4) see table 17 4ah configuration register 2 0000 0000 see table 18 4ch interrupt status register mirror 1 0000 0000 see table 19 4dh interrupt status register mirror 2 0000 0000 see table 20 table 8. register 16h, channel mode register (power ? on default, 00h) bit name r/w description 0 fan1/a in1 r/w clearing this bit to 0 configures pin 5 as fan1 input. setting this bit to 1 configures pin 5 as ain1. power ? on default = 0. 1 fan2/a in2 r/w clearing this bit to 0 configures pin 6 as fan2 input. setting this bit to 1 configures pin 6 as ain2. power ? on default = 0. 2 2.5 v, v ccp2 /d2 r/w clearing this bit to 0 configures pins 17 and 18 to measure v ccp2 and 2.5 v. setting this bit to 1 configures pins 17 and 18 as an input for a second remote temperature ? sensing diode. power ? on default = 0. 3 int. v cc r/w clearing this bit to 0 sets the measurement range for the internal v cc measurement to 3.3 v. setting this bit to 1 sets the internal v cc measurement range to 5.0 v. power ? on default = 0. 4 irq0 en r/w setting this bit to 1 enables pin 24 as an active high interrupt input, provided pins 20 to 24 have been configured as interrupts by setting bit 7 of the channel mode register. power ? on default = 0. 5 irq1 en r/w setting this bit to 1 enables pin 23 as an active high interrupt input, provided pins 20 to 24 have been configured as interrupts by setting bit 7 of the channel mode register. power ? on default = 0. 6 irq2 en r/w setting this bit to 1 enables pin 22 as an active high interrupt input, provided pins 20 to 24 have been configured as interrupts by setting bit 7 of the channel mode register. power ? on default = 0. 7 vid/irq r/w clearing this bit to 0 configures pins 20 to 24 as processor voltage id inputs. setting this bit to 1 configures pins 20 to 24 as interrupt inputs. power ? on default = 0.
ADM1024 http://onsemi.com 26 table 9. register 40h, configuration register 1 (power ? on default, 08h) bit name r/w description 0 start r/w logic 1 enables startup of ADM1024; logic 0 places it in standby mode. caution: the outputs of the interrupt pins will not be cleared if the user writes a 0 to this location after an interrupt has occurred (see ?int clear? bit). at startup, limit checking functions and scanning begins. note, all high and low limits should be set into the ADM1024 prior to turning on this bit (power ? on default = 0). 1 int _enable r/w logic 1 enables the int _output. 1 = enabled 0 = disabled (power ? on default = 0). 2 therm enable r/w 0 = therm disabled 1 = therm enabled 3 int _clear r/w during interrupt service routine (isr), this bit is asserted logic 1 to clear int output without affecting the contents of the interrupt status register. the device will stop monitoring. it will resume upon clearing of this bit. (power ? on default = 0) 4 reset r/w setting this bit generates a low going 45 ms reset pulse at pin 12. this bit is self ? clearing and power ? on default is 0. 5 reserved r/w default = 0 6 therm clr r/w a 1 clears the therm output without changing the status register contents. 7 initialization r/w logic 1 restores power ? on default values to the configuration register, interrupt status registers, interrupt mask registers, fan divisor register, and the temperature configuration register. this bit automatically clears itself since the power ? on default is 0. table 10. register 41h, interrupt status register 1 (power ? on default, 00h) bit name r/w description 0 2.5 v/external temp2 error read only a 1 indicates that a high or low limit has been exceeded. 1 v ccp1 error read only a 1 indicates that a high or low limit has been exceeded. 2 v cc error read only a 1 indicates that a high or low limit has been exceeded. 3 5.0 v error read only a 1 indicates that a high or low limit has been exceeded. 4 internal temp error read only a 1 indicates that a temperature interrupt has been set, or that a high or low limit has been exceeded. 5 external temp1 error read only a 1 indicates that a temperature interrupt has been set, or that a high or low limit has been exceeded. 6 fan1/a in1 error read only a 1 indicates that a high or low limit has been exceeded. 7 fan2/a in2 error read only a 1 indicates that a high or low limit has been exceeded. table 11. register 42h, interrupt status register 2 (power ? on default, 00h) (note 1 and 2) bit name r/w description 0 12 v error read only a 1 indicates a high or low limit has been exceeded. 1 v ccp2 error read only a 1 indicates a high or low limit has been exceeded. 2 reserved read only undefined. 3 reserved read only undefined. 4 chassis error read only a 1 indicates chassis intrusion has gone high. 5 therm interrupt read only indicates that therm pin has been pulled low by an external source. 6 d1 fault read only short or open ? circuit sensor diode d1. 7 d2 fault read only short or open ? circuit sensor diode d2. 1. any time the status register is read out, the conditions (i.e., register) that are read are automatically reset. in the case of the channel priority indication, if two or more channels were out of limits, then another indication would automatically be generated if it was not handled during the isr. 2. in the mask register, the errant voltage interrupt may be disabled until the operator has time to clear the errant condition or set the limit higher/lower.
ADM1024 http://onsemi.com 27 table 12. register 43h, int interrupt mask register 1 (power ? on default, 00h) bit name r/w description 0 2.5 v/ext. temp2 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 1 v ccp1 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 2 v cc r/w a 1 disables the corresponding interrupt status bit for int interrupt. 3 5.0 v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 4 int. temp r/w a 1 disables the corresponding interrupt status bit for int interrupt. 5 ext. temp1 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 6 fan1/a in1 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 7 fan2/a in2 r/w a 1 disables the corresponding interrupt status bit for int interrupt. table 13. register 44h, int interrupt mask register 2 (power ? on default, 00h) bit name r/w description 0 12 v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 1 v ccp2 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 2 reserved r/w powerup default set to low. 3 reserved r/w powerup default set to low. 4 ci r/w a 1 disables the corresponding interrupt status bit for int interrupt. 5 therm (input) r/w a 1 disables the corresponding interrupt status bit for int interrupt. 6 d1 fault r/w a 1 disables the corresponding interrupt status bit for int interrupt. 7 d2 fault r/w a 1 disables the corresponding interrupt status bit for int interrupt. table 14. register 46h, chassis intrusion clear (power ? on default, 00h) bit name r/w description 0?6 reserved read only undefined, always reads as 00h. 7 chassis int. clear r/w a 1 outputs a minimum 20 ms active low pulse on the chassis intrusion pin. the register bit clears itself after the pulse has been output. table 15. register 47h, vid0 ? 3/fan divisor register (power ? on default, 0101(vid3 ? 0)) bit name r/w description 0?3 vid read only the vid<3:0> inputs from processor core power supplies to indicate the operating voltage (e.g., 1.3 v to 3.5 v). 4?5 fan1 divisor r/w sets counter prescaler for fan1 speed measurement. <5:4> = 00 ? divide by 1 <5:4> = 01 ? divide by 2 <5:4> = 10 ? divide by 4 <5:4> = 11 ? divide by 8 6?7 fan2 divisor r/w sets counter prescaler for fan2 speed measurement. <7:6> = 00 ? divide by 1 <7:6> = 01 ? divide by 2 <7:6> = 10 ? divide by 4 <7:6> = 11 ? divide by 8 table 16. register 49h, vid4/device id register (power ? on default, 1000000(vid4)) bit name r/w description 0 vid4 read only vid4 input from pentium 1?7 reserved read only undefined, always reads as 1000 000(vid4)
ADM1024 http://onsemi.com 28 table 17. register 4ah, configuration register 2 (power ? on default, [7:0] = 0x00h) bit name r/w description 0 thermal int mask r/w setting this bit masks the thermal interrupts for the int output only. the therm output will still be generated, regardless of the setting of this bit. 1 ambient temp fan control register write once bit r/w once writing a 1 to this bit will lock in the values set into the ambient temperature automatic fan control register 13h. this register will not be able to be written again until a reset is performed (either por, hard reset, or soft reset). 2 remote temp fan control register write once bit r/w once writing a 1 to this bit will lock in the values set into the remote temperature automatic fan control register 14h. this register will not be able to be written again until a reset is performed (either por, hard reset, or soft reset). 3 therm r/w if this bit is 0, the therm output operates in default mode. interrupt mode if this bit is 1, the therm output operates in acpi mode. 4, 5 reserved read only reserved 6 irq3 en r/w setting this bit to 1 enables pin 21 as an active high interrupt input, provided pins 20 to 24 have been configured as interrupts by setting bit 7 of the channel mode register. power ? on default = 0. 7 irq4 en r/w setting this bit to 1 enables pin 20 as an active high interrupt input, provided pins 20 to 24 have been configured as interrupts by setting bit 7 of the channel mode register. power ? on default = 0. table 18. register 4ch, interrupt status register 1 mirror (power ? on default, [7:0] = 00h) bit name r/w description 0 2.5 v/ext. temp2 error read only a 1 indicates that a high or low limit has been exceeded. 1 v ccp1 error read only a 1 indicates that a high or low limit has been exceeded. 2 v cc error read only a 1 indicates that a high or low limit has been exceeded. 3 5.0 v error read only a 1 indicates that a high or low limit has been exceeded. 4 internal temp error read only a 1 indicates that a temperature interrupt has been set, or that a high or low limit has been exceeded. 5 external temp1 error read only a 1 indicates that a temperature interrupt has been set, or that a high or low limit has been exceeded. 6 fan1/a in1 error read only a 1 indicates that a high or low limit has been exceeded. 7 fan2/a in2 error read only a 1 indicates that a high or low limit has been exceeded. table 19. register 4dh, interrupt status register 2 mirror (power ? on default, [7:0] = 00h) (note 1) bit name r/w description 0 12 v error read only a 1 indicates a high or low limit has been exceeded. 1 v ccp2 error read only a 1 indicates a high or low limit has been exceeded. 2 reserved read only undefined. 3 reserved read only undefined. 4 chassis error read only a 1 indicates chassis intrusion has gone high. 5 therm interrupt read only indicates that therm pin has been pulled low by an external source. 6 d1 fault read only short or open ? circuit sensor diode d1. 7 d2 fault read only short or open ? circuit sensor diode d2. 1. an error that causes continuous interrupts to be generated may be masked in its respective mask register, until the error can be alleviated. ordering information device order number temperature range package type shipping ? ADM1024aruz 0 c to +100 c 24 ? lead tssop 62 tube ADM1024aruz ? reel 0 c to +100 c 24 ? lead tssop 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *the ?z?? suffix indicates pb ? free part.
ADM1024 http://onsemi.com 29 package dimensions 24 lead tssop case 948h ? 01 issue a dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 24x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ADM1024/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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